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HS-82C12RH
March 1996
Radiation Hardened 8-Bit Input/Output Port
Functional Diagram
DS1 DS2 STB CLR MD DATA LATCH AND BUFFER (8) CONTROL AND DEVICE SELECT LOGIC 2 SERVICE REQUEST F.F.
Features
* Devices QML Qualified in Accordance with MIL-PRF-38535 * Detailed Electrical and Screening Requirements are Contained in SMD# 5962-95818 and Intersil' QM Plan - Radiation Hardened CMOS Process - Total Dose 1 x 105 RAD (Si) - Transient Upset > 1 x 108 RAD (Si)/s - Latch-Up Immune EPI-CMOS > 1 x 1012 RAD (Si)/s * * * * * * * * * * * Low Power Dissipation High Noise Immunity Single Power Supply +5V Low Input Load Current 8-Bit Data Register and Buffer Asynchronous Register Clear Service Request Flip-Flop for Interrupt Generation Three-State Outputs Bus-Compatible with HS-80C85RH CPU Electrically Equivalent to Sandia SA3026 Military Temperature Range -55oC to +125oC
INT
3
DI0-7
DO0-7
Pin Description
PIN DI0-DI7 DO0-DO7 DS1, DS2 MD STB INT CLR Data In Data Out Device Select Mode Strobe Interrupt Clear DESCRIPTION
Description
The Intersil HS-82C12RH is a radiation hardened 8-bit input/ output port designed for use with the HS-80C85RH radiation hardened microprocessor. It is manufactured using a selfaligned, junction-isolated EPI-CMOS process and features three-state output buffers and device selection and control logic. A service request flip-flop is included for the generation and control of interrupts to the microprocessor. The device can be used in implement many of the peripheral and input/output functions of a microcomputer system. The HS-82C12RH is pinout- and function- compatible with industry-standard 8212 devices.
Ordering Information
PART NUMBER 5962R9581801QJC 5962R9581801QXC 5962R9581801VJC 5962R9581801VXC HS1-82C12RH/Sample HS9-82C12RH/Sample TEMPERATURE RANGE -55oC to +125oC -55oC to +125oC -55oC to +125oC -55oC to +125oC +25oC +25oC SCREENING LEVEL MIL-PRF-38535 Level Q MIL-PRF-38535 Level Q MIL-PRF-38535 Level V MIL-PRF-38535 Level V Sample Sample PACKAGE 24 Lead SBDIP 24 Lead Ceramic Flatpack 24 Lead SBDIP 24 Lead Ceramic Flatpack 24 Lead SBDIP 24 Lead Ceramic Flatpack DB NA
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
Spec Number File Number
1
518063 3041.2
HS-82C12RH Pinouts
24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T24 TOP VIEW
DS1 1 MD 2 DI0 3 DO0 4 DI1 5 DO1 6 DI2 7 DO2 8 DI3 9 DO3 10 STB 11 GND 12 24 VDD 23 INT 22 DI7 21 DO7 20 DI6 19 DO6 18 DI5 17 DO5 16 DI4 15 DO4 14 CLR 13 DS2
24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F24 TOP VIEW
DS1 MD DI0 DO0 DI1 DO1 DI2 DO2 DI3 DO3 STB GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD INT DI7 DO7 DI6 DO6 DI5 DO5 DI4 DO4 CLR DS2
Spec Number 2
518063
Specifications HS-82C12RH
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VDD+0.3V Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Reliability Information
Thermal Resistance JA JC SBDIP Package . . . . . . . . . . . . . . . . . . . . 55oC/W 14oC/W Ceramic Flatpack Package . . . . . . . . . . . 74oC/W 13oC/W Maximum Package Power Dissipation at +125oC Ambient SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.91W Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W If device power exceeds package dissipation capability, provide heat sinking or derate linearly at the following rate: SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18.2mW/C Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . .13.5mW/C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +1.0V Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VDD -1V to VDD
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER High Input Leakage Current Low Input Leakage Current Low Output Voltage SYMBOL IIH CONDITIONS VDD = 5.25V, VIN = 0V, Pin under test = 5.25V VDD = 5.25V, VIN = 5.25V, Pin under test = 0V VDD = 5.25V, IOL = 2mA GROUP A SUBGROUPS 1, 2, 3 TEMPERATURE -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC MIN MAX 1 UNITS A A
IIL
1, 2, 3
-1
-
VOL
1, 2, 3
-
0.5
V
High Output Voltage
VOH
VDD = 4.75V, IOH = -2mA
1, 2, 3
4.25
-
V A
Static Current
SIDD
VDD = 5.25V, VIN = GND
1, 2, 3
-
100
Functional Tests
FT
VDD = 4.75V and 5.25V, VIH = VDD-1.0V, VIL = 1.0V
7, 8A, 8B
-
-
-
NOTE: All devices are guaranteed at worst case limits and over radiation.
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Data to Output Delay Write Enable to Output Delay Reset to Output Delay Set to Output Delay Clear to Output Delay Output Enable Time Output Disable Time NOTE: 1. Output Timings are measured with the following conditions: CL = 100pF, VIH = 3.75V, and VIL = 1.0V SYMBOL TPD TWE TR TS TC TE TD GROUP A SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 TEMPERATURE -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC MIN MAX 105 200 145 100 135 125 85 UNITS ns ns ns ns ns ns ns
Spec Number 3
518063
Specifications HS-82C12RH
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Input Capacitance SYMBOL CIN CONDITIONS VDD = Open, f = 1MHz, All measurements referenced to device ground VDD = Open, f = 1MHz, All measurements referenced to device ground VDD = 4.75, VIH = 3.75, VIL = 1.0 9, 10, 11 GROUP A SUBGROUPS TEMPERATURE TA = +25oC MIN MAX 8 UNITS pF
Output Capacitance
COUT
TA = +25oC
-
8
pF
Pulse Width
TPW
-55oC, +25oC, +125oC -55oC, +25oC, +125oC -55oC, +25oC, +125oC
-
50
ns
Data Set Up Time
TSET
VDD = 4.75, VIH = 3.75, VIL = 1.0
9, 10, 11
-
30
ns
Data Hold Time
TH
VDD = 4.75, VIH = 3.75, VIL = 1.0
9, 10, 11
-
40
ns
NOTE: The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics.
TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS NOTE: The Post Irradiation test conditions and limits are the same as those listed in Table 1 and Table 2.
Spec Number 4
518063
HS-82C12RH Timing Waveforms
(DS, * DS2)
tE tD 0.5VDD
OUTPUT
VOH VOL
0.5VDD
FIGURE 1. READ TIMING
DATA tPW MD OR (DS, * DS2) tH
tWE
OUTPUT
FIGURE 2. WRITE TIMING
DATA tSET tH
STB OR (DS, * DS2) tPD
OUTPUT
FIGURE 3. DATA SETUP, HOLD, PROPAGATION DELAY TIMING
tPW STB tPW
(DS, * DS2) tR tS INT
FIGURE 4. INTERRUPT TIMING
CLR tC DO
tPW
FIGURE 5. CLEAR TIMING
Spec Number 5
518063
HS-82C12RH Functional Description
Data Latch
The data latch is comprised of eight "D" type flip-flops. The output of each flip-flop will follow the corresponding data input (DI0 - DI7) when the clock (C) is high. The clock input is level sensitive and the data becomes latched when the clock returns low. An asynchronous reset (CLR) is used to clear the latched data. Since the clock (C) overrides the reset (CLR), the data must be in the latched state in order to clear the flip-flops. If the data is not latched (i.e. clock is high) when CLR goes low, then the Q outputs of the data latch will continue to follow the data input, overriding the reset signal.
Mode
the mode input (MD) is used to control the state of the output buffer and to determine the source of the data latch clock (C). When MD is high, the output buffers are enabled and the source of the data latch clock (C) is the device select logic (DS1 * DS2). When MD is low, the state of the output buffer is controlled by the device select logic (DS1 * DS2) and the source of the data latch clock is the strobe (STB) input.
Strobe
The strobe input (STB) is used as the data latch clock (C) when the mode input (MD) is low. The service request flipflop is synchronously set on the negative going edge of STB.
Output Buffer
Three-state buffers are used to provide output drive for the data latch. A high level on the "output buffer enable" control line enables the buffer outputs. When "output buffer enable" is low the buffer outputs are forced to the high-impedance state.
Service Request Flip-Flop
The service request flip-flop is to generate interrupts to microcomputer systems. It is negative edge triggered and asynchronously cleared (reset). The output of the service request flip-flop is AND-gated with the device select logic (DS1 * DS2). The output of the AND gate is the active low interrupt (INT) signal.
Device Select Logic
The inputs DS1 and DS2 are used for device selection. When DS1 is low and DS2 is high, the device is selected. The output buffers are enabled and the service request flipflop is asynchronously cleared when the device is selected.
Spec Number 6
518063
HS-82C12RH Logic Diagram
DEVICE DS1 13 DS2 S STB 11 CLR 14 DI2 7 LATCH CLOCK D E R Q Q TSB 8 DO2 D C Q Q SERVICE REQUEST FLIP-FLOP DI1 5 D E R Q Q TSB 6 SELECT DATA OUT ENABLE LATCH RESET DI0 3 D E R Q Q TSB 4 DO0 INT 23
DO1
DI3 MD 9 2 D E R Q Q TSB
DO3 10
DI4 16 D E R Q Q TSB
DO4 15
DI5 18 D E R Q Q TSB
DO5 17
DI6 20 D E R Q Q TSB
DO6 19
DI7 22 D E R Q Q TSB
DO7 21
TRUTH TABLE 1. DATA OUT STB 0 1 0 1 0 1 0 1 MD 0 0 1 1 0 0 1 1 DS1 * DS2 0 0 0 0 1 1 1 1 DATA OUT EQUALS High Z State High Z State Data Latch Data Latch Data Latch Data In Data In Data In CLR 0 RESET 1 1 1 1
TRUTH TABLE 2. INT DS1 * DS2 0 0 0 1 RESET 0 0 0 STB 0 0 Q* 0 0 1 0 0 INT 1 1 0 0 1
* Internal Service Request Flip-Flop
Spec Number 7
518063
HS-82C12RH Metallization Topology
DIE DIMENSIONS: 90 x 76 x 14 1mils METALLIZATION: Type: AlSi Thickness: 11kA 2kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA
Metallization Mask Layout
HS-82C12RH
(24) VDD (1) DS1 (3) DI0 (2) MD (23) INT
(22) DI7 DO0 (4) DI1 (5)
(21) DO7 (20) DI6
DO1 (6)
(19) DO6
DI2 (7) DO2 (8) DI3 (9)
(18) DI5
(17) DO5 (16) DI4
(15) DO4
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
GND (12)
DO3 (10)
CLR (14)
STB (11)
DS2 (13)
Spec Number 8
518063

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